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Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Read Cycle
When addressed with a read command, the MAX2120
allows the master to read back a single register, or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/ W = 0). The MAX2120 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read (see Table 1 for register addresses). The
slave acknowledges the address. Then, a START condi-
tion is issued by the master, followed by the 7 slave
address bits and a read bit (R/ W = 1). The MAX2120
issues an ACK if the slave address byte is successfully
received. The MAX2120 starts sending data MSB first
with each SCL clock cycle. At the 9th clock cycle, the
master can issue an ACK and continue to read succes-
sive registers, or the master can terminate the transmis-
sion by issuing a NACK. The read cycle does not
terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which registers 0
through 2 are read back.
WRITE
WRITE
WRITE DATA
WRITE DATA
WRITE DATA
START
DEVICE
ADDRESS
1100000
R/ W
0
ACK
—
REGISTER
ADDRESS
0x00
ACK
—
TO REGISTER
0x00
0x0E
ACK
—
TO REGISTER
0x01
0xD8
ACK
—
TO REGISTER
0x02
0x0E1
ACK
—
STOP
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
S
T
A
R
T
DEVICE
ADDRESS
1100000
R/W
0
A
C
K
REGISTER
ADDRESS
00000000
A
C
K
S
T
A
R
T
DEVICE
ADDRESS
1100000
R/W
1
A
C
K
REG 00
DATA
xxxxxxxx
A
C
K
REG 01
DATA
xxxxxxxx
A
C
K
REG 02
DATA
xxxxxxxx
N
A
C
K
S
T
O
P
Figure 3. Example: Receive data from read registers.
16
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